Advances in the semiconductor industry continue to demand the development of more powerful integrated circuits (ICs). As a result, device feature sizes continue to be scaled downward, thereby increasing the speed of the devices as well as the device density that may be exhibited by the integrated circuit. Multilayer structures have been simultaneously developed to allow for increasingly complex interconnect systems to be employed, so that the advanced devices may be interconnected for enhanced performance and system functionality.
In particular, multilayer structures separated by interlayer dielectrics (ILDs) are generally utilized to implement an interconnect system within an IC. Holes opened in the ILD layer(s) allow a metallization layer to extend to other metallization layers thereby producing conductive interlayer interconnects commonly referred to as vias. Variable-depth vias may also be implemented within the multilayer ICs, so as to allow the interconnection between conductive layers that exist at varying depths with respect to one another.
A chemical vapor deposition (CVD) process is typically utilized to deposit a layer of metal, e.g., tungsten (W), over each ILD layer to fill the vias previously formed within the ILD layer. The blanket film of tungsten over each ILD layer may then be removed from the planar surface, e.g., by etching or chemical-mechanical polishing (CMP), thereby leaving only the metallized vias, i.e., tungsten plugs. Typically, a first interconnect layer of the multilayer IC is formed using a single damascene structure, whereby a dielectric layer is deposited over the ILD & W layers, followed by formation of interconnect trenches and filling of these trenches with metal during a metal deposition step. A subsequent CMP process is then utilized to remove the excess metal to form a planar structure having metallized inlays (this is referred to as the single damascene process).
The remaining layers of a multi-level interconnect structure are typically formed using a so-called “dual-damascene structure,” where only a single metallization step is used to simultaneously form the metallized interconnect as well as the metallized vias or plugs. In particular, the vias and interconnect trenches are formed on each layer and then simultaneously filled with metal during a metal deposition step. A subsequent CMP process is then utilized to remove the excess metal to form a planar structure having metallized inlays and metallized vias.
Turning to FIG. 1A, a cross-section of a multi-level interconnect structure is illustrated, whereby the various layers of a semiconductor die are implemented using the, e.g., single/dual damascene processes as discussed above. In particular, interconnect layers 102-110 represent an integer number, N, of interconnect layers that may exist within a multi-layer semiconductor die. A corresponding number of ILD layers 112-120 also exist, whereby the blank portions of ILD layers 112-120 represent dielectric regions utilized to insulate one interconnect layer from another.
The cross-hatched portions of ILD layers 112-120 represent a cross-section of the metallized vias, or plugs, that provide inter-layer connectivity, while the cross-hatched portions of interconnect layers 102-110 represent a cross-section of the metallized interconnect traces that provide intra-layer conductivity. As such, signals propagating on, e.g., interconnect layer 102, may traverse interconnect layers, e.g., 104-108, using the corresponding interconnect traces and vias of ILD layers, e.g., 112-118, to propagate to interconnect layer, e.g., 110.
Such a multi-level interconnect structure may be utilized within the IC of FIG. 1B, whereby conductive metallization layer 122 may receive signal 140 for propagation to component 124 using signal path 126, where signal path 126 traverses the multi-level interconnect structure as discussed above in relation to FIG. 1A. Component 124 may then be made conductive to propagate signal 140 through signal path 134 through each of the various layers of the multi-level interconnect structure as illustrated. Component 128 may also be made conductive to similarly propagate signal 140 using signal paths 136-138 as shown.
The IC of FIG. 1B may, therefore, be suited for an application known as power segmentation, whereby components 124 and 128 may represent power switching components to selectively propagate operational power throughout the IC as necessary. In such an instance, conductive metallization layer 122 may represent a global power supply plane to receive signal 140, which represents the operational power signal provided by an external power supply (not shown) that may be utilized by the semiconductor die during normal operating conditions. Each of components 124 and 128 may then be made selectively conductive to propagate operational power signal 140 from conductive metallization layer 122 throughout the IC as necessary.
Should the IC of FIG. 1B represent a programmable logic device (PLD), such as a field programmable gate array (FPGA), certain logic portions within the IC may remain unused, i.e., non-configured. Operational power to the unused logic, therefore, need not be supplied. As such, power switch, e.g., 128, may be made non-conductive to deprive the unused logic portions that are electrically coupled to signal path 138 of operational power. Alternately, the IC of FIG. 1B may represent a device that exhibits a “power-save” mode, whereby portions of the IC may be deprived of operational power during the power-save mode, i.e., by using the non-conductive attributes of power switch elements 124 and 128 to prohibit propagation of the operational power signal and thereby reducing the power consumption.
As can be seen by inspection of FIG. 1B, however, implementation of power segmentation requires that sufficient conductive traces and inter-layer vias be implemented within the multi-level interconnect structure of the IC to achieve the programmable propagation paths that are required by a power segmentation implementation. For example, sufficient conductive traces and inter-layer vias are required to first propagate operational power signal 140 received at conductive metallization layer 122 of external interconnect portion 130 to semiconductor device implementation portion 132 using signal path 126. Power switching component 124 may then be utilized to propagate the operational power signal vertically upward through the multi-level interconnect structure of the IC using signal path 134, so as to provide operational power to the corresponding interconnected logic segments that receive operational power from signal path 134.
Should other logic segments require operational power, then power switching component 128 may be utilized to receive the operational power signal from conductive metallization layer 122 via signal path 136 and then provide the operational power signal upward through the multi-level interconnect structure of the IC, so as to provide operational power to the corresponding logic segment that receives operational power from signal path 138. Other logic segments (not shown) within the multi-level interconnect structure may receive operational power in a similar manner.
As can be seen, therefore, power segmentation using the multi-level interconnect structure of FIG. 1B has several disadvantages. First, power switching components 124 and 128 are typically implemented with feature sizes that are several orders of magnitude larger than core logic components and, therefore, require a significant portion of semiconductor die area for their implementation. For example, the width of transistors utilized to implement switching components 124 and 128 may be several hundreds to several thousands of microns, so as to minimize the on-resistance of the transistors, thereby minimizing the drop in operational voltage magnitude that they provide. As such, a significant amount of semiconductor die area is consumed by power switching components 124 and 128, which could otherwise be used by other core logic functions implemented within semiconductor device implementation portion 132.
A routing penalty is also realized by the multi-level interconnect structure of FIG. 1B. In particular, each operational power signal that is to be provided to each logic segment within the IC must traverse at least two vertical paths through the IC; a first path to propagate the operational power signal from the external interconnect portion 130 to the semiconductor device implementation portion 132, and a second path to propagate the operational power signal from the semiconductor device implementation portion 132 to the logic segment that requires the operational power signal. Such a vertically implemented interconnect, however, may well be in conflict with the data and clock lines that may be predetermined within the IC, such as is the case with a PLD. In addition, an area penalty is also sustained, since the interconnect traces and inter-layer vias each require a portion of semiconductor area on each layer of the multi-level interconnect structure of FIG. 1B.
Efforts continue, therefore, to provide power segmentation architectures that would otherwise be impossible, or at least prohibitively costly, to implement within complex ICs such as PLDs.